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Winbond Clock Generator W83195WG-301 W83195CG-301 For ATI P4 Chipset
Date:
Feb/27/2006
Revision: 0.6
W83195WG-301/W83195CG-301
STEPLESS FOR ATI P4 CLOCK GENERATOR W83195WG-301/W83195CG-301 Data Sheet Revision History
Pages 1 2 3 4 5 6 7 8 9 10 n.a. 8,13 Dates 01/20/2006 02/27/2006 Version 0.5 0.6 Web Version n.a. n.a. Main Contents
All of the versions before 0.50 are for internal use.
Modify default register value in blue text.
Please note that all data and specifications are subject to change without notice. All the trademarks of products and companies mentioned in this data sheet belong to their respective owners. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales.
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Publication Release Date: Feb 2006 Revision 0.6
W83195WG-301/W83195CG-301
STEPLESS FOR ATI P4 CLOCK GENERATOR TABLE OF CONTENT
1. 2. 3. 4. 5. 6. 7. GENERAL DESCRIPTION ......................................................................................................... 1 PRODUCT FEATURES .............................................................................................................. 1 PIN CONFIGURATION ............................................................................................................... 2 BLOCK DIAGRAM ...................................................................................................................... 2 PIN DESCRIPTION..................................................................................................................... 3 FREQUENCY SELECTION BY HARDWARE OR SOFTWARE ................................................ 5 I2C CONTROL AND STATUS REGISTERS ............................................................................... 6 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 7.13 7.14 7.15 7.16 7.17 7.18 7.19 7.20 7.21 7.22 8. Register 0: ( Default : 00h ) ......................................................................................................6 Register 1: ( Default : XXh) ......................................................................................................6 Register 2: ( Default : 03h ) ......................................................................................................7 Register 3: ( Default : 03h ) ......................................................................................................7 Register 4: ( Default : FEh) ......................................................................................................8 Register 5: ( Default : 02h ) ......................................................................................................9 Register 6: ( Default : FFh )......................................................................................................9 Register 7: Winbond Chip ID - Project Code Register ( Default : 06h )...............................10 Register 8: ( Default :D0h )..................................................................................................10 Register 9: ( Default : 7Ah )....................................................................................................11 Register 10: Reserved ( Default : 3Bh ).................................................................................11 Register 11: ( Default : 0Eh )..................................................................................................11 Register 12: ( Default : XXh ) .................................................................................................11 Register 13: ( Default : 3Fh )..................................................................................................12 Register 14: ( Default : D0h ) .................................................................................................12 Register 15: ( Default : 5Ch ) .................................................................................................13 Register 16: ( Default : 24h ) ..................................................................................................13 Register 17: Reserved ( Default : 07h ) .................................................................................14 Register 18: Reserved ( Default : 7Ah ).................................................................................14 Register 19: ( Default : 04h ) ..................................................................................................14 Register 20: ( Default : 88h ) ..................................................................................................15 Register 21: ( Default : ECh ).................................................................................................15
Table3: SRC & ATIG Frequency Selection Table..............................................................................16 ACCESS INTERFACE .............................................................................................................. 17 8.1 8.2 8.3 8.4 Block Write protocol ...............................................................................................................17 Block Read protocol ...............................................................................................................17 Byte Write protocol .................................................................................................................17 Byte Read protocol.................................................................................................................17 Publication Release Date: Feb 2006 Revision 0.6
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W83195WG-301/W83195CG-301
STEPLESS FOR ATI P4 CLOCK GENERATOR
9. SPECIFICATIONS .................................................................................................................... 18 9.1 9.2 9.3 9.4 9.5 9.6 9.7 9.8 9.9 10. 11. 12. ABSOLUTE MAXIMUM RATINGS .......................................................................................18 General Operating Characteristics ........................................................................................18 Skew Group timing clock........................................................................................................18 CPU 0.7V Electrical Characteristics ......................................................................................19 SRC 0.7V Electrical Characteristics ......................................................................................19 9.6 ATIG 0.7V Electrical Characteristics ...............................................................................19 PCI Electrical Characteristics.................................................................................................20 USB Electrical Characteristics ...............................................................................................20 REF Electrical Characteristics ...............................................................................................20
ORDERING INFORMATION..................................................................................................... 21 HOW TO READ THE TOP MARKING...................................................................................... 21 PACKAGE DRAWING AND DIMENSIONS.............................................................................. 22
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Publication Release Date: Feb 2006 Revision 0.6
W83195WG-301/W83195CG-301
STEPLESS FOR ATI P4 CLOCK GENERATOR
1. GENERAL DESCRIPTION
The W83195WG-301/W83195CG-301 is a Clock Synthesizer for ATI P4 serial chipsets. W83195WG301/ W83195CG-301 provides all clocks required for the high-speed microprocessor and provides step-less frequency programming and 32 different frequencies of CPU, PCI, and SRC clocks setting, all clocks are externally selectable with smooth transitions. W83195WG-301/ W83195CG-301 also support CPU TURBO function when system has heavy loading. The W83195WG-301/ W83195CG-301 has watchdog timer and reset output pin to support auto-reset when systems hanging caused by improper frequency setting. It also support CPU TURBO function when system has heavy loading. The W83195WG-301/W83195CG-301 provides I2C serial bus interface to program the registers to enable or disable each clock outputs and provides programmable S.S.T. scale to reduce EMI. The W83195WG-301/W83195CG-301 accepts a 14.318 MHz reference crystal as its input and runs on a 3.3V supply.
2. PRODUCT FEATURES
* * * * * * * * * * * * * * 3 pair current-mode Differential clock outputs for CPU. 6 pair current-mode Differential clock outputs for SRC. 2 pair current-mode Differential clock outputs for ATIG programmable. 1 PCI clock output. 1 48 MHz clock output for USB. 3 14.318MHz REF clock outputs. Smooth frequency switch with selections from 100 to 400MHz. Step-less frequency programming. CPU TURBO function support. I2C 2-wire serial interface and support byte read/write and block read/write. Programmable S.S.T. scale to reduce EMI in M/N mode. Programmable registers to enable/disable each output and select modes. Programmable clock outputs slew rate control and skew control. Watch Dog Timer and RESET# output pins
* 56 pin TSSOP/SSOP package.
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Publication Release Date: Feb 2006 Revision 0.6
W83195WG-301/W83195CG-301
STEPLESS FOR ATI P4 CLOCK GENERATOR
3. PIN CONFIGURATION
XIN XOUT VDD48 *TURBO_SEL/USB_48 GND *VTT_PG/PD# SCLK SDATA RESET# & CLKREQA# & TURBO/&CLKREQB# SRCT7 SRCC7 VDDSRC GND SRCT6 SRCC6 SRCT5 SRCC5 GND VDDSRC SRCT4 SRCC4 SRCT3 SRCC3 GND ATIGT1 ATIGC1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 VDDREF GND & FSA/REF0 & FSB/REF1 & FSC/REF2 VDDPCI & CK410#/PCICLK0 GND *CPU_STOP# CPUT0 CPUC0 VDDCPU GND CPUT1 CPUC1 CPUT2_ITP CPUC2_ITP VDDA GNDA IREF GND VDDSRC SRCT0 SRCC0 VDDATI GND ATIGT0 ATIGC0
#: Active low *: Internal pull up resistor 120K to VDD &: Internal Pull-down resistor 120K to GND
4. BLOCK DIAGRAM
2
A TIG LO O P U SB LO O P C PU LO O P Spread Spectrum XIN XO U T XTA L O SC
D ivider
2
ATIG T 0:1 A TIG C 0:1
D ivider & Sync
48M H z
3
R EF 0:2
3 3 V CO CLK
C PU T 0:2 C PU C 0:2
SR C LO O P Spread Spectrum
M /N /R atio ROM
D ivider & Snyc
6 6
SRC T 0,3:7 SR C C 0,3:7
FS(A:C ) C R#_(A :B ) *VTT_PG C K410#
Latch & PO R
PC I0
*TU RB O_SEL & TUR B O C PU_STO P# PD #
C ontrol Logic &C onfig R egister
R ESET# IREF
475
SD ATA SCLK
I2C Interface
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Publication Release Date: Feb 2006 Revision 0.6
W83195WG-301/W83195CG-301
STEPLESS FOR ATI P4 CLOCK GENERATOR
5. PIN DESCRIPTION
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 XIN XOUT VDD48
*TURBO_SEL/USB_48
Pin Name
Type IN OUT
Description
Crystal output at 14.318MHz nominally with internal loading capacitors (18pF). Crystal input with internal loading capacitors (18pF) and feedback resistors.
PWR Power supply for USB_48 I/O Real time input pin to change frequency to a pre-programmed. 3.3V USB 48Mhz clock output. Notifies CK410 to sample latched input or power down mode Serial clock of I2C 2-wire control interface. Serial data of I2C 2-wire control interface. Dynamic output control 0 = active, 1 = inactive Turbo function control. Dynamic output control 0 = active, 1 = inactive
GND *VTT_PG/PD# SCLK SDATA RESET#
&
PWR Ground pin IN IN I/O
OUT System reset signal when the watchdog is time out. IN IN
CLKREQA#
&
&
TURBO/ CLKREQB#
SRCT7 SRCC7 VDDSRC GND SRCT6 SRCC6 SRCT5 SRCC5 GND VDDSRC SRCT4 SRCC4 SRCT3 SRCC3 GND ATIGT1 ATIGC1
OUT 0.7V current mode differential clock output for SRC OUT 0.7V current mode differential clock output for SRC PWR Power supply for SRC PWR Ground pin OUT 0.7V current mode differential clock output for SRC OUT 0.7V current mode differential clock output for SRC OUT 0.7V current mode differential clock output for SRC OUT 0.7V current mode differential clock output for SRC PWR Ground pin PWR Power supply for SRC OUT 0.7V current mode differential clock output for SRC OUT 0.7V current mode differential clock output for SRC OUT 0.7V current mode differential clock output for SRC OUT 0.7V current mode differential clock output for SRC PWR Ground pin OUT 0.7V current mode differential clock output for ATIG OUT 0.7V current mode differential clock output for ATIG Publication Release Date: Feb 2006 Revision 0.6
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W83195WG-301/W83195CG-301
STEPLESS FOR ATI P4 CLOCK GENERATOR
29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 ATIGC0 ATIGT0 GND VDDATIG SRCC0 SRCT0 VDDSRC GND IREF GNDA VDDA CPUC2_ITP CPUT2_ITP CPUC1 CPUT1 GND VDDCPU CPUC0 CPUT0 *CPU_STOP# GND
&
OUT 0.7V current mode differential clock output for ATIG OUT 0.7V current mode differential clock output for ATIG PWR Ground pin PWR Power supply for ATIG OUT 0.7V current mode differential clock output for SRC OUT 0.7V current mode differential clock output for SRC PWR Power supply for SRC PWR Ground pin Deciding the reference current for the differential pairs. The pin OUT was connected to the precision resistor tied to ground to decide the appropriate current; 475 ohm is the standard value. PWR PWR Ground pin for PLL core. 3.3V power supply for PLL core.
OUT 0.7V current mode differential clock output for CPUC2 OUT 0.7V current mode differential clock output for CPUT2 OUT 0.7V current mode differential clock output for CPUC1 OUT 0.7V current mode differential clock output for CPUT1 PWR Ground pin PWR Power supply for CPU OUT 0.7V current mode differential clock output for CPUC0 OUT 0.7V current mode differential clock output for CPUT0 IN Stop selected CPUCLK.
PWR Ground pin I/O FS Table select latch input pin / 3.3V PCI clock output. 0 = CK410 FS Table, 1 = CK409 FS Table
CK410#/PCICLK0
VDDPCI
& & &
PWR Power supply for PCI I/O I/O I/O FSC CPU frequency select/3.3V REF 14.318Mhz clock output. FSB CPU frequency select/3.3V REF 14.318Mhz clock output. FSA CPU frequency select/3.3V REF 14.318Mhz clock output.
FSC/REF2 FSB/REF1 FSA/REF0
GND VDDREF
PWR Ground pin PWR Power supply for REF
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Publication Release Date: Feb 2006 Revision 0.6
W83195WG-301/W83195CG-301
STEPLESS FOR ATI P4 CLOCK GENERATOR
6. FREQUENCY SELECTION BY HARDWARE OR SOFTWARE
This frequency table is used at power on latched FS [2:0] value or software programming at SSEL [4:0] (Register 0 bit 7 ~ 3). If FS [2:0] no any external circuit to modify power on status the Gray shading is Hardware default frequency.
BIT 7 FS4
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
BIT 6 FS3
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
BIT 5 FS2
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
BIT 4 FS1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
BIT 3 FS0
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
CPU (MHZ)
266.68 133.34 200.01 166.59 333.17 100.00 400.01 200.06 266.68 133.34 200.01 166.59 333.17 100.00 400.01 200.06 100.00 133.34 200.01 166.59 199.90 266.68 400.01 333.30 100.00 133.34 200.01 166.59 199.90 266.68 400.01 333.30
SRC (MHZ)
100.00 100.00 100.00 111.06 111.06 100.00 100.00 100.03 100.00 100.00 100.00 111.06 111.06 100.00 100.00 100.03 100.00 100.00 100.00 111.06 99.95 100.00 100.00 111.10 100.00 100.00 100.00 111.06 99.95 100.00 100.00 111.10
PCI (MHZ)
33.33 33.33 33.33 33.32 33.32 33.33 33.33 33.34 33.33 33.33 33.33 33.32 33.32 33.33 33.33 33.34 33.33 33.33 33.33 33.32 33.32 33.33 33.33 33.33 33.33 33.33 33.33 33.32 33.32 33.33 33.33 33.33
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Publication Release Date: Feb 2006 Revision 0.6
W83195WG-301/W83195CG-301
STEPLESS FOR ATI P4 CLOCK GENERATOR
7. I2C CONTROL AND STATUS REGISTERS
(The register No. is increased by 1 if use byte data read/write protocol)
7.1
BIT
Register 0: ( Default : 00h )
AFFECTED PIN/ FUNCTION NAME(S) PWD AFFECTED PIN / FUNCTION DESCRIPTION TYPE
7 6 5 4 3 2
SSEL<4> SSEL<3> SSEL<2> SSEL<1> SSEL<0> EN_SSEL
0 0 0 0 0 0 Enable software table selection FS[4:0]. 0 = Hardware table setting (Jump mode). 1 = Software table setting through Bit7~3 (Jumpless mode) Enable spread spectrum mode under clock output. 0 = Spread Spectrum mode disable 1 = Spread Spectrum mode enable After watchdog timeout 0 = Reload the hardware FS [4:0] latched pins setting. 1 = Reload the desirable frequency table selection defined at Reg-5 Bit 4~0. R/W Software frequency table selection through I2C R/W
1
SPSPEN
0
R/W
0
EN_SAFE_FREQ
0
R/W
7.2
BIT
Register 1: ( Default : XXh)
AFFECTED PIN/ FUNCTION NAME(S) PWD FUNCTION DESCRIPTION TYPE
7
CPUEN<2>
1
6
CPUEN<1>
1
5 4 3 2 1 0
CPUEN<0> CK410_N_BACK Reserved FS2_BACK FS1_BACK FS0_BACK
1 X X X X X
CPUT/C_ITP output control 1: Enable 0: Disable CPUCLKT1/C1 output control 1: Enable 0: Disable CPUCLKT0/C0 output control 1: Enable 0: Disable Power on latched value of FS4 pin. Default : 0 Reserved Power on latched value of FS2 pin. Default : 0 Power on latched value of FS1 pin. Default : 0 Power on latched value of FS0 pin. Default : 0
R/W
R/W
R/W R R R R R
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Publication Release Date: Feb 2006 Revision 0.6
W83195WG-301/W83195CG-301
STEPLESS FOR ATI P4 CLOCK GENERATOR
7.3
BIT
Register 2: ( Default : 03h )
AFFECTED PIN/ FUNCTION NAME(S) PWD FUNCTION DESCRIPTION TYPE
7
CLREQA7#_Ctr
0
SRCCLK7 is controlled by the CLREQA# pin 1: Controllable 0: Uncontrollable SRCCLK6 is controlled by the CLREQA# pin 1: Controllable 0: Uncontrollable SRCCLK5 is controlled by the CLREQA# pin 1: Controllable 0: Uncontrollable SRCCLK4 is controlled by the CLREQA# pin 1: Controllable 0: Uncontrollable SRCCLK3 is controlled by the CLREQA# pin 1: Controllable 0: Uncontrollable SRCCLK0 is controlled by the CLREQA# pin 1: Controllable 0: Uncontrollable Reserved Reserved
R/W
6
CLREQA6#_Ctr
0
R/W
5
CLREQA5#_Ctr
0
R/W
4
CLREQA4#_Ctr
0
R/W
3
CLREQA3#_Ctr
0
R/W
2 1 0
CLREQA0#_Ctr Reserved Reserved
0 1 1
R/W R/W R/W
7.4
BIT
Register 3: ( Default : 03h )
AFFECTED PIN/ FUNCTION NAME(S) PWD FUNCTION DESCRIPTION TYPE
7
CLREQB7#_Ctr
0
SRCCLK7 is controlled by the CLREQB# pin 1: Controllable 0: Uncontrollable SRCCLK6 is controlled by the CLREQB# pin 1: Controllable 0: Uncontrollable SRCCLK5 is controlled by the CLREQB# pin 1: Controllable 0: Uncontrollable SRCCLK4 is controlled by the CLREQB# pin 1: Controllable 0: Uncontrollable
R/W
6
CLREQB6#_Ctr
0
R/W
5
CLREQB5#_Ctr
0
R/W
4
CLREQB4#_Ctr
0
R/W
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Publication Release Date: Feb 2006 Revision 0.6
W83195WG-301/W83195CG-301
STEPLESS FOR ATI P4 CLOCK GENERATOR
3 CLREQB3#_Ctr 0 SRCCLK3 is controlled by the CLREQB# pin 1: Controllable 0: Uncontrollable SRCCLK0 is controlled by the CLREQB# pin 1: Controllable 0: Uncontrollable PCI0 output control 1: Enable 0: Disable Reserved R/W
2
CLREQB0#_Ctr
0
R/W
1 0
PCIEN Reserved
1 1
R/W R/W
7.5
BIT
Register 4: ( Default : FEh)
AFFECTED PIN/ FUNCTION NAME(S) PWD FUNCTION DESCRIPTION TYPE
7
CPU2S_EN
1
CPU_STOP# pin control. 1: Enable CPUCLK2 stop feature 0: Disable stop feature CPU_STOP# pin control. 1: Enable CPUCLK1 stop feature 0: Disable stop feature CPU_STOP# pin control. 1: Enable CPUCLK0 stop feature 0: Disable stop feature PREF2 output control 1: Enable 0: Disable PREF1 output control 1: Enable 0: Disable PREF0 output control 1: Enable 0: Disable PUSB48 output control 1: Enable 0: Disable Reserved
R/W
6
CPU1S_EN
1
R/W
5
CPU0S_EN
1
R/W
4
REFEN<2>
1
R/W
3
REFEN<1>
1
R/W
2
REFEN<0>
1
R/W
1
F48EN
1
R/W
0
Reserved
0
R/W
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Publication Release Date: Feb 2006 Revision 0.6
W83195WG-301/W83195CG-301
STEPLESS FOR ATI P4 CLOCK GENERATOR
7.6
BIT
Register 5: ( Default : 02h )
AFFECTED PIN/ FUNCTION NAME(S) PWD FUNCTION DESCRIPTION TYPE
7
Reserved
0
Reserved Program this bit => 1 : Enable Watchdog Timer feature. 0 : Disable Watchdog Timer feature. Enable WD sequence => Program this bit to 1 firstly, then program the Reg-20 to start the counting Read-back this bit => During timer count down the bit read back to 1. If count to zero, this bit read back to 0. Read Back only. Timeout Flag. 1 : Watchdog has ever started and count to zero. 0 : a.) Watchdog is restarted and counting. b.) Power on default state
R/W
6
CNT_EN
0
R/W
5
WD_TIMEOUT
0
R
4 3 2 1 0
SAF_FREQ<4> SAF_FREQ<3> SAF_FREQ<2> SAF_FREQ<1> SAF_FREQ<0>
0 0 0 1 0 These bits will be reloaded in Reg-0 to select frequency table. As the watchdog is timeout and EN_SAFE_FREQ=1.
R/W
7.7
BIT
Register 6: ( Default : FFh )
AFFECTED PIN/ FUNCTION NAME(S) PWD FUNCTION DESCRIPTION TYPE
7
SRCEN<7>
1
6
SRCEN<6>
1
5
SRCEN<5>
1
4
SRCEN<4>
1
SRC7 output control 1: Enable 0: Disable SRC6 output control 1: Enable 0: Disable SRC5 output control 1: Enable 0: Disable SRC4 output control 1: Enable 0: Disable
R/W
R/W
R/W
R/W
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Publication Release Date: Feb 2006 Revision 0.6
W83195WG-301/W83195CG-301
STEPLESS FOR ATI P4 CLOCK GENERATOR
3 SRCEN<3> 1 SRC3 output control 1: Enable 0: Disable ATIG1 output control 1: Enable 0: Disable ATI clock can't be controlled by CLKREQ# pins ATIG0 output control 1: Enable 0: Disable ATI clock can't be controlled by CLKREQ# pins SRC0 output control 1: Enable 0: Disable R/W
2
ATIGEN<1>
1
R/W
1
ATIGEN<0>
1
R/W
0
SRCEN<0>
1
R/W
7.8
BIT
Register 7: Winbond Chip ID - Project Code Register ( Default : 06h )
AFFECTED PIN/ FUNCTION NAME(S) PWD FUNCTION DESCRIPTION TYPE
7 6 5 4 3 2 1 0
CHIP_ID [7] CHIP_ID [6] CHIP_ID [5] CHIP_ID [4] CHIP_ID [3] CHIP_ID [2] CHIP_ID [1] CHIP_ID [0]
0 0 0 0 0 1 1 0
Winbond Chip ID.W83195CG/WG-301 (BA5A06). Winbond Chip ID. Winbond Chip ID. Winbond Chip ID. Winbond Chip ID. Winbond Chip ID. Winbond Chip ID. Winbond Chip ID.
R R R R R R R R
7.9
BIT
Register 8: ( Default :D0h )
AFFECTED PIN/ FUNCTION NAME(S) PWD FUNCTION DESCRIPTION TYPE
7 6 5 4 3 2 1 0
NVAL<8> NVAL<9> MVAL<5> MVAL<4> MVAL<3> MVAL<2> MVAL<1> MVAL<0>
1 1 0 1 0 0 0 0
Programmable N divisor value. Bit 7 ~0 are defined in the Register 9. Programmable N divisor value. Bit 7 ~0 are defined in the Register 9.
R/W R/W
Programmable M divisor
R/W
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Publication Release Date: Feb 2006 Revision 0.6
W83195WG-301/W83195CG-301
STEPLESS FOR ATI P4 CLOCK GENERATOR
7.10 Register 9: ( Default : 7Ah )
BIT AFFECTED PIN/ FUNCTION NAME(S) PWD FUNCTION DESCRIPTION TYPE
7 6 5 4 3 2 1 0
NVAL<7> NVAL<6> NVAL<5> NVAL<4> NVAL<3> NVAL<2> NVAL<1> NVAL<0>
0 1 1 1 1 0 1 0 Default value follow FS=0 Programmable N divisor bit 7 ~0. The bit 8,9 is defined in Register 8. R/W
7.11 Register 10: Reserved ( Default : 3Bh ) 7.12 Register 11: ( Default : 0Eh )
BIT AFFECTED PIN/ FUNCTION NAME(S) PWD FUNCTION DESCRIPTION TYPE
7 6 5 4 3 2 1 0
SPH VAL<3> SPH VAL<2> SPH VAL<1> SPH VAL<0> SPL VAL<3> SPL VAL<2> SPL VAL<1> SPL VAL<0>
0 0 0 0 1 1 1 0 Spread Spectrum Down Counter bit 3 ~ bit 0 2's complement representation. Ex: 1 -> 1111 ; 2 -> 1110 ; 7 -> 1001 ; 8 -> 1000 Spread Spectrum Up Counter bit 3 ~ bit 0. R/W
7.13 Register 12: ( Default : XXh )
BIT AFFECTED PIN/ FUNCTION NAME(S) PWD FUNCTION DESCRIPTION TYPE
7 6 5 4 3 2 1 0
Reserved KVAL<9> KVAL<5> KVAL<4> KVAL<3> KVAL<2> KVAL<1> KVAL<0>
0 X X X X X X X
Reserved Define the PCI divider ratio Table-2 integrate the all divider configuration Define the SRC divider ratio Refer to Table-2 Define the CPU divider ratio Refer to Table-2
R/W R/W R/W
R/W
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Publication Release Date: Feb 2006 Revision 0.6
W83195WG-301/W83195CG-301
STEPLESS FOR ATI P4 CLOCK GENERATOR
Table-2 CPU, SRC, PCI divider ratio selection Table PCI LSB Bit5 MSB Bit2/ Bit4/ Bit9 1 Div24 Div30 Div8 Div10 Div8 Div8 Div8 Div8 0 0 Reserved 1 Div20 0 Reserved Bit3 1 Div6 00 Div2 01 Div3 Bit1,0 10 Div4 11 Div6 SRC CPU
7.14 Register 13: ( Default : 3Fh )
BIT AFFECTED PIN/ FUNCTION NAME(S) PWD FUNCTION DESCRIPTION TYPE
7
EN_MN_PROG
0
6 5 4 3 2 1 0
Reserved Reserved Reserved IVAL<3> IVAL<2> IVAL<1> IVAL<0>
0 1 1 1 1 1 1
0: Output frequency depend on frequency table 1: Program all clock frequency by changing M/N value The equation is VCO =14.318MHz*(N+4)/ M. Once the watchdog timer timeout, the bit will be clear. Then the frequency will be decided by hardware default FS<4:0> or desired frequency select SAF_FREQ[4:0] depend on EN_SAFE_FREQ (Reg0 - bit0). Reserved Reserved
R/W R/W
Charge pump current selection
R/W
7.15 Register 14: ( Default : D0h )
BIT AFFECTED PIN/ FUNCTION NAME(S) PWD FUNCTION DESCRIPTION TYPE
7 6 5 4 3 2 1 0
Reserved Reserved SPCNT<5> SPCNT<4> SPCNT<3> SPCNT<2> SPCNT<1> SPCNT<0>
1 1 0 1 0 0 0 0
Reserved Reserved
R/W R/W
Spread Spectrum Programmable time, the resolution is 280ns. Default period is 11.8us
R/W
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Publication Release Date: Feb 2006 Revision 0.6
W83195WG-301/W83195CG-301
STEPLESS FOR ATI P4 CLOCK GENERATOR
7.16 Register 15: ( Default : 5Ch )
BIT AFFECTED PIN/ FUNCTION NAME(S) PWD FUNCTION DESCRIPTION TYPE
7 6
INV_CPU Reserved
0 1
Invert the CPUCLKT1/0 phase 0: Default 1: Inverse Reserved CPUT/ SRCT/ ATIG output state in during POWER DOWN assertion. 1: Driven (2*Iref) 0: Tristate (Floating) CPUT/ SRCT/ ATIG output state in during STOP Mode assertion. 1: Driven (6*Iref) 0: Tristate (Floating) Complementary parts always tri-state (floating) in power down or stop mode. Reserved
R/W R/W
5
DRI_CONT
0
R/W
4 3 2 1 0
Reserved Reserved Reserved Reserved Reserved
1 1 1 0 0
R/W
Reserved
R/W
7.17 Register 16: ( Default : 24h )
BIT AFFECTED PIN/ FUNCTION NAME(S) PWD FUNCTION DESCRIPTION TYPE
7
INV_SRC
0
6 5 4 3 2 1 0
INV_PCI CSKEW<2> CSKEW<1> CSKEW<0> PSKEW<2> PSKEW<1> PSKEW<0>
0 1 0 0 1 0 0
Invert the SRC phase 0: Default 1: Inverse Invert the HTT & PCI phase 0: Default 1: Inverse CPUCLKT1 to CPUCLKT0 skew control Skew resolution is 300ps The decision of skew direction is same as CSKEW<2:0> setting CPU1 to PCI skew control Skew resolution is 300ps The decision of skew direction is same as PSKEW<2:0> setting
R/W
R/W
R/W
R/W
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Publication Release Date: Feb 2006 Revision 0.6
W83195WG-301/W83195CG-301
STEPLESS FOR ATI P4 CLOCK GENERATOR
7.18 Register 17: Reserved ( Default : 07h )
BIT AFFECTED PIN/ FUNCTION NAME(S) PWD FUNCTION DESCRIPTION TYPE
7 6 5
Reserved Reserved Reserved
0 0 0
Reserved Reserved Reserved Real mode overclocking CPU. 1: Enable
R/W R/W R/W
4
TURBO_EN
0
0: Disable This bit should be enable before using real mode overclocking feature.
R/W
3 2 1 0
Reserved Reserved NtVAL<9> NtVAL<8>
0 1 1
Reserved Reserved Dynamic programmable N divisor bit 9,8.
R/W
R/W
1
7.19 Register 18: Reserved ( Default : 7Ah )
BIT AFFECTED PIN/ FUNCTION NAME(S) PWD FUNCTION DESCRIPTION TYPE
7 6 5 4 3 2 1 0
NtVAL<7> NtVAL<6> NtVAL<5> NtVAL<4> NtVAL<3> NtVAL<2> NtVAL<1> NtVAL<0>
0 1 1 1 1 0 1 0 Default value follow FS=2 Dynamic programmable N divisor bit 7 ~0. The bit 9,8 is defined in Register 17. R/W Real-time overclocking
7.20 Register 19: ( Default : 04h )
BIT AFFECTED PIN/ FUNCTION NAME(S) PWD FUNCTION DESCRIPTION TYPE
7 6 5 4 3
SRC_FS<4> SRC_FS<3> SRC_FS<2> SRC_FS<1> SRC_FS<0>
0 0 0 0 0 SRC frequency table. See Table-3. SRC_FS<4> also is spread spectrum enable bit.
R/W R/W R/W
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Publication Release Date: Feb 2006 Revision 0.6
W83195WG-301/W83195CG-301
STEPLESS FOR ATI P4 CLOCK GENERATOR
2 1 0 CENTERSKEW<2> CENTERSKEW<1> CENTERSKEW<0> 1 0 0 CPU1 center skew control Skew resolution is 300ps The decision of skew direction is same as CENTERSKEW<2:0> setting R/W
7.21 Register 20: ( Default : 88h )
BIT AFFECTED PIN/ FUNCTION NAME(S) PWD FUNCTION DESCRIPTION TYPE
7 6 5 4 3 2 1 0
Reserved SEC<6> SEC<5> SEC<4> SEC<3> SEC<2> SEC<1> SEC<0>
1 0 0 0 1 0 0 0
Reserved
R/W
Setting the down count depth (Failure decision). One bit resolution represent 250ms. Default time depth is 8*250ms = 2.0 second. If the watchdog timer is counting, this register will return present down count value.
R/W
7.22 Register 21: ( Default : ECh )
BIT AFFECTED PIN/ FUNCTION NAME(S) PWD FUNCTION DESCRIPTION TYPE
7 6
Reserved CPU2SRC_SYNC
1 1
Reserved CPU align with SRC 1 : Enable 0 : Disable CPU align with PCI 1 : Enable 0 : Disable Reserved Reserved CPU1 to SRC skew control Skew resolution is 300ps The decision of skew direction is same as SRCSKEW<2:0> setting
R/W R/W
5 4 3 2 1 0
CPU2PCI_SYNC Reserved Reserved SRCSKEW<2> SRCSKEW<1> SRCSKEW<0>
1 0 1 1 0 0
R/W R/W R/W R/W R/W
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Publication Release Date: Feb 2006 Revision 0.6
W83195WG-301/W83195CG-301
STEPLESS FOR ATI P4 CLOCK GENERATOR
Table3: SRC & ATIG Frequency Selection Table
BIT 7 FS4
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
BIT 6 FS3
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
BIT 5 FS2
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
BIT 4 FS1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
BIT 3 FS0
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
SRC,ATIG (MHZ)
100.00 100.00 100.00 100.00 101.00 101.00 101.00 101.00 102.00 102.00 102.00 102.00 104.00 104.00 104.00 104.00 100.00 100.00 100.00 100.00 101.00 101.00 101.00 101.00 102.00 102.00 102.00 102.00 104.00 104.00 104.00 104.00
SPREAD(%)
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5
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Publication Release Date: Feb 2006 Revision 0.6
W83195WG-301/W83195CG-301
STEPLESS FOR ATI P4 CLOCK GENERATOR
8. ACCESS INTERFACE
The W83195BR-301 provides I2C Serial Bus for microprocessor to read/write internal registers. In the W83195BR-301 is provided Block Read/Block Write and Byte-Data Read/Write protocol. The I2C address is defined at 0xD2. The register number is increased by one if using byte data read/write protocol. Example: In block mode, byte number of program register is 1 In byte mode, byte number of program register is 2 (Byte number of block mode +1)
8.1
Block Write protocol
8.2
Block Read protocol
## In block mode, the command code must filled 8'h00
8.3
Byte Write protocol
8.4
Byte Read protocol
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Publication Release Date: Feb 2006 Revision 0.6
W83195WG-301/W83195CG-301
STEPLESS FOR ATI P4 CLOCK GENERATOR
9. SPECIFICATIONS
9.1 ABSOLUTE MAXIMUM RATINGS
Stresses greater than those listed in this table may cause permanent damage to the device. Precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. Subjection to maximum conditions for extended periods may affect reliability. Unused inputs must always be tied to an appropriate logic voltage level (Ground or VDD). Parameter Absolute 3.3V Core Supply Voltage Absolute 3.3V I/O Supple Voltage Operating 3.3V Core Supply Voltage Operating 3.3V I/O Supple Voltage Storage Temperature Ambient Temperature Operating Temperature Input ESD protection (Human body model) Rating -0.5V to +4.6V - 0.5V to + 4.6V 3.135V to 3.465V 3.135V to 3.465V - 65C to + 150C - 55C to + 125C 0C to + 70C 2000V
9.2
General Operating Characteristics
Parameter Symbol VIL VIH VOL VOH Idd Cin Cout Lin 2.4 350 5 6 7 2.0 0.4 Min Max 0.8 Units Vdc Vdc Vdc Vdc mA pF pF nH CPU = 100 to 400 MHz PCI = 33.3 Mhz with load 10pF Test Conditions
VDD= 3.3V 5 %, TA = 0C to +70C,
Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Operating Supply Current Input pin capacitance Output pin capacitance Input pin inductance
9.3
Skew Group timing clock
Parameter Min Max 100 125 250 1000 Units ps ps ps ps Test Conditions Measure Crossing point Measure Crossing point Measured at 1.5V Measured at 1.5V Publication Release Date: Feb 2006 Revision 0.6
VDD = 3.3V 5 %, TA = 0C to +70C, Cl=10pF CPU pair to CPU pair Skew SRC pair to SRC pair Skew PCI to PCI Skew 48MHz to 48MHz Skew
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W83195WG-301/W83195CG-301
STEPLESS FOR ATI P4 CLOCK GENERATOR
9.4 CPU 0.7V Electrical Characteristics
VDDC= 3.3V 5 %, TA = 0C to +70C, Test load Rs=33, Rp=49.9 Cl=2pF, Vol=0.175V, Voh=0.525V, Vr=475, IREF=2.32mA, Ioh=6*IREF Parameter Rise Time Fall Time Absolute crossing point Voltages Voltage High Voltage Low Cycle to Cycle jitter Duty Cycle 45 Min 175 175 250 660 -150 100 55 Max 700 700 550 850 Units ps ps mV mV mV ps % Test Conditions Measure Single Ended waveform Measure Single Ended waveform Measure Single Ended waveform Measure Single Ended waveform Measure Single Ended waveform Measure Differential waveform Measure Differential waveform
9.5
SRC 0.7V Electrical Characteristics
VDDS= 3.3V 5 %, TA = 0C to +70C, Test load Rs=33, Rp=49.9 Cl=2pF, Vol=0.175V, Voh=0.525V, Vr=475, IREF=2.32mA, Ioh=6*IREF Parameter Rise Time Fall Time Absolute crossing point Voltages Voltage High Voltage Low Cycle to Cycle jitter Duty Cycle 45 Min 175 175 250 660 -150 100 55 Max 700 700 550 850 Units ps ps mV mV mV ps % Test Conditions Measure Single Ended waveform Measure Single Ended waveform Measure Single Ended waveform Measure Single Ended waveform Measure Single Ended waveform Measure Differential waveform Measure Differential waveform
9.6 9.6 ATIG 0.7V Electrical Characteristics
VDDATIG= 3.3V 5 %, TA = 0C to +70C, Test load Rs=33, Rp=49.9 Cl=2pF, Vol=0.175V, Voh=0.525V, Vr=475, IREF=2.32mA, Ioh=6*IREF Parameter Rise Time Fall Time Absolute crossing point Voltages Voltage High Voltage Low Cycle to Cycle jitter Duty Cycle 45 Min 175 175 250 660 -150 100 55 Max 700 700 550 850 Units ps ps mV mV mV ps % Test Conditions Measure Single Ended waveform Measure Single Ended waveform Measure Single Ended waveform Measure Single Ended waveform Measure Single Ended waveform Measure Differential waveform Measure Differential waveform
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Publication Release Date: Feb 2006 Revision 0.6
W83195WG-301/W83195CG-301
STEPLESS FOR ATI P4 CLOCK GENERATOR
9.7 PCI Electrical Characteristics
VDDP= 3.3V 5 %, TA = 0C to +70C, Test load, Cl=10pF, Parameter Rise Time Fall Time Cycle to Cycle jitter Duty Cycle Pull-Up Current Min Pull-Up Current Max Pull-Down Current Min Pull-Down Current Max 30 38 45 -33 -33 Min 500 500 Max 2000 2000 250 55 Units ps ps ps % mA mA mA mA Test Conditions Vol=0.4V, Voh=2.4V Voh=2.4V, Vol=0.4V Measured at 1.5V Measured at 1.5V Vout=1.0V Vout=3.135V Vout=1.95V Vout=0.4V
9.8 USB Electrical Characteristics
VDD48= 3.3V 5 %, TA = 0C to +70C, Test load, Cl=10pF, Parameter Rise Time Fall Time Long term jitter Duty Cycle Pull-Up Current Min Pull-Up Current Max Pull-Down Current Min Pull-Down Current Max 29 27 45 -29 -23 Min 500 500 Max 2000 2000 300 55 Units ps ps ps % mA mA mA mA Test Conditions Vol=0.4V, Voh=2.4V Voh=2.4V, Vol=0.4V Measured at 1.5V Measured at 1.5V Vout=1.0V Vout=3.135V Vout=1.95V Vout=0.4V
9.9 REF Electrical Characteristics
VDDR= 3.3V 5 %, TA = 0C to +70C, Test load, Cl=10pF, Parameter Rise Time Fall Time Cycle to Cycle jitter Duty Cycle Pull-Up Current Min Pull-Up Current Max Pull-Down Current Min Pull-Down Current Max 30 38 45 -33 -33 Min 500 500 Max 2000 2000 700 55 Units ps ps ps % mA mA mA mA Test Conditions Vol=0.4V, Voh=2.4V Voh=2.4V, Vol=0.4V Measured at 1.5V Measured at 1.5V Vout=1.0V Vout=3.135V Vout=1.95V Vout=0.4V
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Publication Release Date: Feb 2006 Revision 0.6
W83195WG-301/W83195CG-301
STEPLESS FOR ATI P4 CLOCK GENERATOR
10. ORDERING INFORMATION Part Number W83195WG-301 W83195CG-301 Package Type 56 PIN TSSOP 56 PIN SSOP Production Flow Commercial, 0C to +70C Commercial, 0C to +70C
11. HOW TO READ THE TOP MARKING
W83195WG-301 28051234 604LBABA W83195CG-301 28051234 604GBABA
1st line: Winbond logo and the type number: W83195WG-301/W83195CG-301 2nd line: Tracking code 2 8051234 2: wafers manufactured in Winbond FAB 2
8051234: wafer production series lot number 3rd line: Tracking code 604 L B A BA
604: packages made in '2006, week 04 L: assembly house ID; O means OSE, G means GR , L means Lingsen B: Internal use code A: IC revision BA: mask version All the trademarks of products and companies mentioned in this data sheet belong to their respective owners.
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Publication Release Date: Feb 2006 Revision 0.6
W83195WG-301/W83195CG-301
STEPLESS FOR ATI P4 CLOCK GENERATOR
12. PACKAGE DRAWING AND DIMENSIONS
56 PIN TSSOP-240mil
56 PIN SSOP-300mil
.035 .045
DIMENSION IN MM
.045 .055 0.40/0.50 DIA
DIMENSION IN INCH
SYMBOL
E
END VIEW
HE
A A1 A2 b c D HE E e L L1 Y
MIN. NOM MAX. MIN. NOM 0.095 0.101 2.41 2.57 2.79 0.41 0.008 0.012 0.20 0.30 0.088 0.090 2.34 2.24 2.29 0.25 0.20 0.34 0.008 0.010 0.13 0.25 0.005 0.720 0.400 0.292 0.020 0.024 18.2 18.42 18.54 9 10.16 10.31 10.41 7.42 0.51 0.61 7.52 0.64 0.81 1.40 7.59 0.76 1.02 0.08 8
MAX. 0.110 0.016 0.092 0.0135 0.010
TOP VIEW
SEE DETAIL "A"
c
D
A2
A
Y SEATING PLANE e b
SIDE VIEW A1 PARTING LINE
0.725 0.730 0.406 0.410 0.296 0.299 0.025 0.030 0.032 0.040 0.055 0.003 8
c
0
0
L L1
DETAIL"A"
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Publication Release Date: Feb 2006 Revision 0.6
W83195WG-301/W83195CG-301
STEPLESS FOR ATI P4 CLOCK GENERATOR
Important Notice
Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Further more, Winbond products are not intended for applications wherein failure of Winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales.
Headquarters
No. 4, Creation Rd. III, Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5770066 FAX: 886-3-5665577 http://www.winbond.com.tw/
Winbond Electronics Corporation America Winbond Electronics (Shanghai) Ltd
2727 North First Street, San Jose, CA 95134, U.S.A. TEL: 1-408-9436666 FAX: 1-408-5441798 27F, 2299 Yan An W. Rd. Shanghai, 200336 China TEL: 86-21-62365999 FAX: 86-21-62365998
Taipei Office
9F, No.480, Rueiguang Rd., Neihu District, Taipei, 114, Taiwan, R.O.C. TEL: 886-2-8177-7168 FAX: 886-2-8751-3579
Winbond Electronics Corporation Japan
7F Daini-ueno BLDG, 3-7-18 Shinyokohama Kohoku-ku, Yokohama, 222-0033 TEL: 81-45-4781881 FAX: 81-45-4781800
Winbond Electronics (H.K.) Ltd.
Unit 9-15, 22F, Millennium City, No. 378 Kwun Tong Rd., Kowloon, Hong Kong TEL: 852-27513100 FAX: 852-27552064
Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.
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Publication Release Date: Feb 2006 Revision 0.6

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